1. Field of the Invention
The present invention relates to the fabrication of integrated circuits and, more specifically, to a method and apparatus for measuring and calibrating the registration between overlying layers on the surface of a semiconductor wafer.
2. Description of the Prior Art
The fabrication of complex semiconductor devices involves multiple processing steps. Multiple patterned layers of different materials are applied to a substrate to create the desired electronic semiconductor device. The different layers overlie each other and must be accurately registered to ensure proper operation of the semiconductor device. Displacement between corresponding features on different layers can degrade the performance of the device or can cause the device to be totally inoperative. As semiconductor devices have become increasingly complex, the feature dimensions have been correspondingly reduced. This reduction in feature dimensions has reduced acceptable tolerances or displacements between the various layers within a semiconductor device.
Most semiconductor devices are now made using photolithographic techniques. Such techniques involve the exposure of the surface of a semiconductor body to a particular pattern, and the subsequent formation or development of that pattern into permanent form through the use of wet or dry etching techniques that create various regions and structures on the surface of the semiconductor body. As is well known in the state of the art, photolithographic procedures require that a mask be used to define those portions of the semiconductor material where various elements of semiconductor devices are to be located. Because different parts or elements of these semiconductor devices must be located at precisely defined distances from each other, it is desirable that each of the masks used in forming the semiconductor device is aligned with respect to the other masks as precisely as possible both in vertical and in horizontal directions.
These operations of alignment are typically performed visually by examining the surface of the semiconductor wafer and the mask under a microscope.
Standard practice in positioning and aligning a wafer during wafer processing operations is to use an inspection pattern on the semiconductor wafer to determine the degree of alignment of a first device layer.
A great number of the processing steps used during the manufacturing of semiconductor devices are based on the application of photolithographic exposures. Of key importance in making successive photolithographic exposures is that successive layers of patterns are accurately aligned with respect to each other. The degree of misalignment that can occur between successive photolithographic exposures is known as pattern overlay, overlay than represents the degree of misalignment that occurs between successive layers of patterns on thin film electronic structures and the preceding layer.
The term overlay represents the relative location of features formed during different steps of the semiconductor wafer processing sequence. The overlay is a numeric quantity that is defined at every location on the substrate as the difference between a numerical value indicative of a position or location on the first formed portion of a semiconductor structure on a substrate and a numeric quantity of the corresponding point on a following or second formed portion of a semiconductor structure. Perfect alignment between the first and the second portion of the semiconductor structure requires that the overlay, as defined here, be equal to zero.
One approach in aligning wafer is to use an independent process layer, the so-called zeroth layer, as the source of reference and to align all process layers to this zeroth layer. Techniques and measuring tools are provided to measure the degree of shift that occurs in the overlay of the successive layers and patterns. All these techniques use alignment patterns of a particular design that are applied to both successive and preceding layers. The first layer used in this alignment sequence does, by its very nature, not have a reference point or pattern. This may lead to considerable problems of alignment in subsequent alignment steps.
FIG. 1 shows the Prior Art method of placing reference marks 10 on the surface of wafer 12, this top view of the wafer surface represents the previously highlighted zeroth layer process. This process places the reference marks on the surface of the substrate. Successive formations of patterns use marks 10 as alignment marks, it is a given that the overlay of the marks 10 for the successive patterns that are formed on the semiconductor substrate is zero. That is the marks 10 are, going from the preceding to the following deposition of patterns, in perfect alignment. Measured is the overlay within the successive patterns while these patterns are being created.
FIG. 2a shows the Prior Art creation of a preceding pattern 14 formed on the wafer 12 by use of prior art method of chip manufacturing using two intersecting patterns 18 and 20. FIG. 2b shows a magnification of the pattern 14 as representative of the first pattern that is created on the surface of the semiconductor substrate. This pattern is created at scribe lines within the surface of the semiconductor substrate and serves as the reference pattern for the measurement of the alignment of the following patterns.
FIG. 3a shows the Prior Art formation of a following or second pattern 16 on the surface of the semiconductor substrate as representative of the second pattern that is created on the surface of the semiconductor substrate. The pattern 16 is created by use of prior art method of chip manufacturing using two intersecting patterns 22 and 24. The pattern 16 (FIG. 3a) is roughly in the same geometric location on the wafer surface as the previously highlighted first pattern (pattern 14, FIG. 2a). FIG. 3b shows a magnified image where the reference pattern (pattern 14, FIG. 2a) is superimposed over the pattern that is representative of the second pattern (pattern 16, FIG. 3a). The smaller square 26 is patterned in the second pattern in the same geometric location as the reference square 28.
It is clear from FIG. 3b that in measuring values for x1, x2, y1 and y2 accurate conclusions can be drawn relating to the relative position of the second pattern (pattern 16, FIG. 3a) with respect to the first or reference pattern (patter 14, FIG. 2a). It is also clear that the alignment accuracy of following layers can be determined in the same manner.
The use of marks on the mask and on the wafer is known to facilitate alignment between the various masks. This approach however can be very time consuming and is influenced by human error. The present invention therefore teaches a method that is both simple and dependable, thus contributing to increased product reliability and a considerable improvement in product yield.
U.S. Pat. No. 5,617,340 (Cresswell et al.) shows a method for measuring overlay and for calibrating image tools.
U.S. Pat. No. 5,280,437 (Corliss) shows a method for direct calibration of registration measurement systems.
U.S. Pat. No. 4,571,538 (Chow) shows a mask alignment measurement structure.
U.S. Pat. No. 4,538,105 (Ausschnitt) discloses an overlay test wafer.
In accordance with the present invention, it is an objective of the present invention to facilitate wafer alignment procedures.
Another objective of the present invention is to eliminate the need for using standard or reference wafers presently used for wafer alignment.
Yet another objective of the present invention is to allow for quick and dependable validation of wafer alignment during scheduled Preventive Maintenance.
Yet another objective of the present invention is to allow for frequent and dependable verification of wafer alignment during semiconductor manufacturing operations.
Yet another objective of the present invention is to verify the reliability of wafer alignment.
Yet another objective of the present invention is to decrease the overall cost of manufacturing semiconductor devices.
Yet another objective of the present invention is to simplify wafer alignment procedures by requiring no more that one reference mark on the control wafer.
In accordance with the indicated objectives of the present invention, the invention teaches a method of overlaying two images and from this overlay observe and measure the accuracy of the alignment of the wafer. Wafer misalignment can be readily corrected based on the results of these observations. Alignment marks are provided on the surface of the wafer that is being validated for accuracy of alignment. The key point of the invention is that double exposure is performed on the same wafer to validate alignment between two reference marks. The relative positioning of the two reference marks with respect to each other determines the amount of overlay of the wafer that is being evaluated for proper positioning. The term overlay as used here indicates the accuracy by which a wafer handling tool positions a wafer within that tool.